This invention relates to a metallic contact for semiconductor devices, and more specifically relates to a novel semiconductor contact and process for its manufacture.
Metal contacts must be made to the surface of silicon wafers or chips which may have junction patterns therein which define particular kinds of semiconductor devices. The metallizing process should be capable of making ohmic contact to silicon regardless of the conductivity type of the silicon and should have low lateral impedance. Moreover, the metallizing should survive temperatures which might be encountered in subsequent manufacturing steps of the semiconductor device manufacturing process. The contact system should also be resistant to chemical etching processes which may be subsequently used to complete the manufacture of a particular device and should be resistant to thermal fatigue which might be experienced during the operation of the device. Finally, the contact system should be easily solderable to electrical leads or other contact coatings.
Metallizing systems which are presently known do not satisfy all of the above characteristics. For example, nickel-chromium-nickel-silver systems are known where the silver is an easily solderable top metal. These systems frequently tend to bubble off the silicon substrate and delaminate at the nickel-silver interface. Moreover, such metallizing does not survive subsequent process steps which may raise the temperature of the substrate to about 650.degree. C.
Another commonly used contact metal is aluminum which bonds well to a silicon surface. However, if devices employing an aluminum contact are later subjected to an alloying operation or some other high temperature operation, the aluminum will diffuse into the surface to form P-type silicon. Thus, the contact may not be useful in devices in which the surface beneath the contact should remain of the N-type.
A contact system is disclosed in copending application Ser. No. 447,761, identified above, which consists of sequential layers of nickel, chromium, nickel and silver applied to the etched surface of a silicon device. In polished silicon, for example, it is believed that an oxygen saturated layer, which may not be easily sensed, exists on the bare treated silicon which is to receive metallization. If this layer is allowed to remain undistured during formation of a nickel-silicide layer at the silicon surface, it is believed that oxygen atoms in the involved region become highly mobile, and diffuse upward to become trapped at the nickel-silver interface. The final result is an oxidized film which destroys the nickel-silver interface and delamination results. Thus, from 1 to 3 microns is etched away from the silicon surface before applying the first nickel coating. Preferably, 2 microns are etched away.
Immediately following the etching step, the first layer of nickel is evaporated, in a high vacuum evaporation chamber, onto the treated silicon surface to a thickness from 125 Angstroms to 1,000 Angstroms. The first nickel layer forms a silicide in the vacuum chamber if there is a moderate degree of substrate heating (100.degree. C. is more than sufficient) and if there is a very clean silicon surface.
A chromium diffusion barrier having a thickness of about 1,000 Angstroms was next formed. Thereafter, a second nickel layer having a thickness of about 4,000 Angstroms is applied atop the chromium diffusion barrier. This second nickel layer was used to guarantee against the leaching of a subsequent metal layer down to the underlying chromium layer. Thereafter, a solderable silver layer of about 6 microms thick is applied over the second nickel layer.
While the above-described system has worked much better than other contact systems, it has been found that the metallization can degrade during the alloying cycle, and the bonding strength between the very thin nickel silicide and the top three metallization layers is weakened. This can result in unreliable gate bonding when applied to thyristor manufacture, due to a brittle metal to silicon interface. It was also found that the process could give rise to poor blocking and dv/dt yields, high V.sub.gt, and occasional pilling and bubbling of the metallization from the silicon substrate.